iverilog -o multiplier_tb multiplier.v tb_multiplier.v vvp multiplier_tb gtkwave dump.vcd | Architecture | LUTs (approx, 7-series) | Max Freq (MHz) | Power | Best for | |---------------|-------------------------|----------------|--------|-------------------------| | * operator | 0 (uses DSP48) | 450+ | Low | FPGA with DSP slices | | Array | 250-300 | 150 | Medium | ASIC, no DSP FPGA | | Sequential | 50-80 | 200 | Low | Low-area, slow designs | | Booth | 180-220 | 250 | Medium | Signed multiplication | | Wallace tree | 300-350 | 300 | High | High-speed DSP, ASIC |
module wallace_tree_8bit ( input [7:0] A, B, output [15:0] P ); // Step 1: generate partial products wire [7:0] pp[0:7]; genvar i, j; generate for(i = 0; i < 8; i = i+1) begin assign pp[i] = 8A[i] & B; end endgenerate // Step 2: reduction using full/half adders (not shown in full) // The tree would reduce 8 vectors to 2 vectors (sum and carry) wire [15:0] sum_vec, carry_vec; 8bit multiplier verilog code github
module sequential_multiplier_8bit ( input clk, rst, start, input [7:0] a, b, output reg [15:0] product, output reg done ); reg [2:0] count; reg [7:0] multiplicand, multiplier; reg [15:0] acc; always @(posedge clk or posedge rst) begin if (rst) begin count <= 0; done <= 0; product <= 0; acc <= 0; end else if (start) begin count <= 0; multiplicand <= a; multiplier <= b; acc <= 0; done <= 0; end else if (!done && count < 8) begin if (multiplier[0]) acc <= acc + 8'b0, multiplicand; multiplicand <= multiplicand << 1; multiplier <= multiplier >> 1; count <= count + 1; end else if (count == 8 && !done) begin product <= acc; done <= 1; end end endmodule iverilog -o multiplier_tb multiplier
initial begin errors = 0; for (i = 0; i < 256; i = i + 1) begin for (j = 0; j < 256; j = j + 1) begin a = i; b = j; #10; if (product !== i*j) begin $display("Error: %d * %d = %d, but got %d", i, j, i*j, product); errors = errors + 1; end end end $display("Simulation done. Errors: %d", errors); $finish; end endmodule output [15:0] P )
module array_multiplier_8bit ( input [7:0] A, B, output [15:0] P ); wire [7:0] pp0, pp1, pp2, pp3, pp4, pp5, pp6, pp7; wire [15:0] sum_stage0, sum_stage1, sum_stage2, sum_stage3; // Generate partial products (AND gates) assign pp0 = 8A[0] & B; assign pp1 = 8A[1] & B; assign pp2 = 8A[2] & B; assign pp3 = 8A[3] & B; assign pp4 = 8A[4] & B; assign pp5 = 8A[5] & B; assign pp6 = 8A[6] & B; assign pp7 = 8A[7] & B;